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Oki Electric's Industry-First Technique Reduces ESD Protection Circuit Design Time by One-Third
[Reference]
Diagram of ESD protection design technique using Mixed-Mode simulation
This diagram shows the ESD protection technique based on Mixed-Mode simulation. This technique involves performing a device experiment test to fulfill target performance parameters such as threshold voltage, drive current, and voltage between source/drain. To obtain ESD parameter, it then prepares the Test Element Group (TEG)*1, which systematically retains variables such as gate length and width for each device to be used in the ESD protection network. The ESD parameter is extracted by measuring the Time Domain Reflection- Transmission Line Pulsing (TDR-TLP)*2 of the completed device. Using the Mixed-Mode simulation that reproduces the ESD parameter, it predicts the current path on the protection circuit network when the ESD input wave is applied, then optimizes device size and resistance value. The information obtained is reflected in layout design as changes in wiring length and device intervals.
[Glossary]
- *1 TEG (Test Element Group)
- A category of evaluation patterns for process and design distinguished by its set of functions. Used primarily to assess the performance of a device or circuit or to check for problems occurred on the full-chip stage.
- *2 TDR-TLP (Time Domain Reflection- Transmission Line Pulsing)
- Using a coaxial cable for high-frequency waves achieves a narrow and stable pulse. Engineers can examine the characteristics of the semiconductor protection circuit by observing incident, reflected, and passing waves. Gradually applying different voltages and plotting the characteristics of voltage and current leads to an understanding of breakdown current and destroy current.
Information in the press releases is current on the date of the press announcement, but is subject to change without prior notice.
